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IPC-TM-650 2.6.3.5
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IPC-TM-650 2.6.3.5 January 1, 2004 Bare Board Cleanliness by Surface Insulation Resistance
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Description / Abstract:
This test method is used to characterize the cleanliness of
printed wiring board fabrication processes by determining the
degradation of electrical insulation resistance under conditions of
high temperature and humidity.
This test method examines the cleanliness of a test substrate prior to solder mask application, after solder mask application, and after any final metalization and/or surface finish operation (e.g., HASL or OSP), and may be used to demonstrate the cleanliness of internal layers of a mulitilayer board prior to lamination.
This test method examines the cleanliness of a test substrate prior to solder mask application, after solder mask application, and after any final metalization and/or surface finish operation (e.g., HASL or OSP), and may be used to demonstrate the cleanliness of internal layers of a mulitilayer board prior to lamination.